1. Technical Field
This disclosure relates generally to integer arithmetic, and more specifically to performing extended multiplies without a carry flag.
2. Description of the Related Art
Most processors implement multiply operations as native instructions. These instructions are typically implemented based on the size of the processor datapath. For example, a 32-bit processor is often configured to accept 32-bit inputs and deliver a 64-bit multiplied result. Another approach is to provide two different multiply instructions, one of which provides the lower 32 bits of the 64-bit product and the other of which provides the upper 32 bits of the 64-bit product.
In order to support even larger multiplies, some multipliers provide carry flags or bits to allow stitching together portions of the larger multiply. For example, multiplication of 64-bit input operands may be performed using a multiplier that supports input operands having a maximum size of 32 bits by performing multiple 32-bit multiplications and passing a carry flag to subsequent multiplications. Using this approach, the smaller multiplies are dependent on the carry flag, and a special register for the carry flag typically must be implemented and tracked.